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GPU tensor cores for fast arithmetic reductions
| dc.contributor.author | Navarro, Cristóbal A. | |
| dc.contributor.author | Carrasco, Roberto | |
| dc.contributor.author | Barrientos, Ricardo | |
| dc.contributor.author | Riquelme, Javier A. | |
| dc.contributor.author | Vega, Raimundo | |
| dc.date.accessioned | 2020-11-17T18:55:10Z | |
| dc.date.available | 2020-11-17T18:55:10Z | |
| dc.date.issued | 2021 | |
| dc.identifier.uri | http://repositorio.ucm.cl/handle/ucm/3222 | |
| dc.description.abstract | This article proposes a parallel algorithm for computing the arithmetic reduction of $n$ numbers as a set of matrix-multiply accumulate (MMA) operations that are executed simultaneously by GPU tensor cores. The analysis, assuming tensors of size $m \times m$ , shows that the proposed algorithm has a parallel running time of $T(n)=5 log_{m^2}{n}$ and a speedup of $S=\frac{4}{5} log_{2}{m^2}$ over a canonical parallel reduction. Experimental performance results on a Tesla V100 GPU show that the tensor-core based approach is energy efficient and runs up to $\sim 3.2 \times$ and $2\times$ faster than a standard GPU-based reduction and Nvidia's CUB library, respectively, while keeping the numerical error below 1 percent with respect to a double precision CPU reduction. The chained design of the algorithm allows a flexible configuration of GPU thread-blocks and the optimal values found through experimentation agree with the theoretical ones. The results obtained in this work show that GPU tensor cores are relevant not only for Deep Learning or Linear Algebra computations, but also for applications that require the acceleration of large summations. | es_CL |
| dc.language.iso | en | es_CL |
| dc.rights | Atribución-NoComercial-SinDerivadas 3.0 Chile | * |
| dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/cl/ | * |
| dc.source | IEEE Transactions on Parallel and Distributed Systems, 32(1), 72-84 | es_CL |
| dc.subject | Arithmetic reduction | es_CL |
| dc.subject | GPU computing | es_CL |
| dc.subject | Tensor cores | es_CL |
| dc.subject | Matrix multiply accumulate | es_CL |
| dc.subject | Parallel reduction | es_CL |
| dc.title | GPU tensor cores for fast arithmetic reductions | es_CL |
| dc.type | Article | es_CL |
| dc.ucm.facultad | Facultad de Ciencias de la Ingeniería | es_CL |
| dc.ucm.indexacion | Scopus | es_CL |
| dc.ucm.indexacion | Isi | es_CL |
| dc.ucm.uri | ieeexplore.ieee.org/document/9147055 | es_CL |
| dc.ucm.doi | doi.org/10.1109/TPDS.2020.3011893 | es_CL |
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